QUESTION: 1
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of
the following statements is TRUE? (VA is the virtual address and PA is the physical address)
A. VA == PA; No address translations; instructions and data are not cached
B. VA! = PA; No address translations; instructions may be cached but not data
C. VA == PA; Address translations take place; data may be cached but not instructions
D. VA == PA; No address translations; instructions may be cached but not data
Answer(s): D
QUESTION: 2
In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being
handled, it is in which of the following states?
A. Inactive
B. Active
C. Pending
D. Edge-triggered
Answer(s): C
QUESTION: 3
A simple system comprises of the following memory map:
Flash - 0x0 to 0x7FFF
RAM - 0x10000 to 0X17FFF
When conforming to the ABI, which of the following is a suitable initial value for the stack
pointer?
A. Top address of RAM (0x18000)
B. Top address of flash (0x8000)
C. Bottom address of RAM (0x10000)
D. Bottom address of flash (0x0000)
Answer(s): A
QUESTION: 4
A program running on a development board that is connected to a host using a debugger
can access a file on the host by using:
A. Memory mapping
2
Overview of the EN0-001 ARM Accredited Engineer Exam Exam
The EN0-001 ARM Accredited Engineer examination validates foundational architectural proficiency for systems architects and embedded engineers working within the ARM ecosystem. Candidates must demonstrate deep technical mastery of the ARMv7-A and ARMv8-A instruction set architectures, including pipeline execution, memory management units, and cache coherency protocols. Assessment domains encompass low-level software integration, interrupt handling, exception modeling, and power management optimization strategies. Professionals must articulate technical nuances regarding AArch64 state transitions, trust zones, and virtualization extensions. Furthermore, the exam evaluates the practical application of AMBA bus protocols, debugging interfaces like CoreSight, and the configuration of hardware-software interfaces necessary for high-performance SoC development.